Power efficient parallel signal processing chip for radio astronomy

Type: Master's Assignment
Contacts: André KokkelerGerard Smit
Student: Simon Dirlek
Project:  CRISP
Location: CAES, University of Twente

Context

For the coming two decades, radio telescopes are planned which are one to two orders of magnitude more sensitive than those of the current generation. With these telescopes it will be possible to probe much further into the universe. Examples of such new-generation telescopes are ASTRON's Low Frequency Array (LOFAR) [1] currently under construction in the Netherlands, and the Square Kilometer Array [2], an international telescope which is currently in a concept study phase.

 

Within these instruments, large amounts of data will be processed digitally, distributed, and further processed in a flexible way. The main signal processing operations on the data consist of filtering, Fast Fourier Transforms (FFTs), beamforming and correlation. In the current LOFAR designs, off the shelf components are used for this, since the numbers are too small to afford custom chips. Off the shelf components are designed for a broad range of applications and not at all optimized for our application.

For the future astronomical applications, especially for the SKA telescope, a more specific chip solution is desired. As the SKA telescope will be a many antenna-element, distributed system with large bandwidths, an architecture is needed which allows for parallel processing on large amounts of data. In addition, as the number of signal paths in SKA will be very large, power consumption will become a serious issue. In order to meet these challenges, a more cost and power effective implementation of the signal processing operations involved, is needed.

Graduation thesis description

Because of the large processing capacity required within this relatively restricted application area, General Purpose Processors (GPPs) and Digital Signal Processors (DSPs) are too generic to be efficient for this application. Field Programmable Gate Arrays (FPGAs) are suitable for prototyping but are not considered being candidates for final implementation.

On the other side, Application Specific Integrated Circuits (ASICs) are very efficient from a power- and chip area point of view but their design process is costly (both in manpower and production costs) and their flexibility is restricted. Within the CAES chair, coarse grain reconfigurable architectures are researched as viable alternatives.

The purpose of this M.Sc. Thesis work is to develop a coarse grain reconfigurable processor, tailored towards the Radio Astronomy domain. The efficiency should be close to the efficiency of ASIC solutions (say within 10%). However, the architecture should be significantly more flexible, thus suitable for related signal processing domains. Typical DSP blocks that have to be supported efficiently are filterbanks, FFTs, beamforming and Correlations. The assignment will consist of the following stages:

  • Development of the processor concept.
  • Development of the processor array concept.
  • Demonstration of processor array achievements considering filterbanks, FFTs, beamforming and correlations.

References

  1. The LOFAR telescope: http://www.lofar.nl/ and http://www.lofar.org/.
  2. The SKA telescope: http://www.skatelescope.org/
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