Analysis and Design of a Dependability Manager for Self-Aware Dependable SoCs

Type: Master's Assignment
Contacts: Ahmed Ibrahim, MSc., Dr. ir. Hans Kerkhoff
Location: CAES, University of Twente


Computer Architecture, Hardware-Software co-design, ASIP.

Prerequisite knowledge:

Computer architecture, strong knowledge of digital design and VHDL, FPGA design flow, basic knowledge of Java and C, basic compiler concepts, basic TCL understanding.


The current trend of aggressive technology scaling and the increasing reliance on design reuse and automation lead to very complex System-on-Chips (SoCs). Testing and debugging of such complex SoCs is a challenging task. Consequently, embedded instruments have been increasingly integrated into SoCs, not only in order to help in testing and debugging, but also for lifetime dependability management.

In the CAES-TDT group we investigate the on-chip access of embedded instruments for smart, self-aware dependable SoCs. A Dependability Manager (DM) is a system-level IP that is able to access the distributed embedded instruments via reconfigurable scan networks, and use the instruments information for executing dependability applications. One can think of the DM as an Application Specific Instruction-set Processor (ASIP) that executes dependability procedures written in a high level language (C/C++/C#/Java…) along with the instruments access procedures written in IEEE 1687 Procedural Description Language (PDL).

In this MSc. thesis it is required to investigate, design and implement a fully operational Dependability Manager. The DM mainly consists of a processor in its core (e.g. MIPS) and several coprocessors for the network operations (a conceptual architecture -not necessarily adopted- is given in Figure 1). In addition, the student will extend an already developed Procedural Description Language (PDL) cross-compiler [1], in order to enable defining instruments interrupts and linking PDL object code with the compiled high level language dependability procedures and interrupt service routines (Figure 2).


Figure1. Conceptual architecture of the DM

Figure 2. Conceptual compilation flow of the dependability applications

The following tasks are to be performed (along with any other necessary ones) within this thesis work:

  • Literature review on ASIP design methodologies.
  • Analyze the different requirements for the different dependability applications (e.g. self-awareness/adaptiveness, online BIST, fault management), and chose an appropriate high level language for their implementation.
  • Perform a complete hardware-software co-design based on the performed analysis. Then implement your design in both hardware and software.
  • An FPGA demonstrator including the DM and a non-trivial iJTAG network will be performed by the end of the thesis showing a working DM + the compilation flow for a number of dependability applications utilizing instruments interrupts.

Successful completion of this thesis could lead into a joint publication in a very active research area (iJTAG and embedded instrumentation).

For more information, please contact Ahmed Ibrahim: This email address is being protected from spambots. You need JavaScript enabled to view it., Tel: +31534894734, Room: ZI 5034.


[1] M. Zakiy, “HW-SW co-Design of an On-Chip IJTAG Dependability Processor”, University of Twente, MSc. Thesis, 2016

[2] Ahmed Ibrahim and Hans G. Kerkhoff, “Analysis and design of an on-chip retargeting engine for IEEE 1687 networks” 21st IEEE European Test Symposium (ETS), 2016, pp. 1-6.

5G Wireless Communications Testbed

Type: Master's Assignment
Contact: André Kokkeler
Location: CAES, University of Twente

For over a century, communication systems have mainly relied on sinusoidal signals. In previous work, we laid the theoretical foundation for another set of basis signals for wireless communications; Hermite functions. The ultimate goal is to allow more users to communicate simultaneously given a certain amount of bandwidth, time and energy. A GNU Radio set-up has been realized and the first measurements using Hermite functions have been done. In the meantime, ideas have evolved and new signals, based on Hermite functions have been developed. The aim is now to investigate how these signals actually perform. For the experiments, the student will use a software defined radio platform. This platform is open-source and decently documented and is widely used to ‘quickly’ prototype software-defined-radio’s.

We have some basic questions which may function as a starting point. For example, how do the new signal sets compare to the original Hermite signals and a conventional OFDM system (e.g. applied in 802.11 WLAN)? What are your observations, can you compare the performance and explain the differences?

Hybrid Memory Cube (HMC)

Type: Master's Assignment
Contacts: André Kokkeler
Location: CAES, University of Twente


Hybrid Memory Cube is a DRAM memory architecture combining high-speed logic process technology with a stack of through-silicon-via (TSV) bonded memory die. The aim is to increase memory performance and bandwidth in an energy efficient way. One of the application areas that is addressed with this technology is High Performance Computing.

Within the CAES group we have a Hybrid Memory Cube research system at our disposal. The system is Linux based with a GPU-sized Gen 3 PCIe backplane and 2 AC-510 modules (one Xilinx Kintex XCKU060 and one 4 GB HMC on each module).  More information can be found on

The aim of the MSc. assignment is to investigate whether the HMC technology is suitable for power efficient computing within Radio Astronomy. Algorithms to be investigated are the 2D FFT, Gridding and Degridding.

Reconfigurable architecture for a mixed-signal feedback controller

Type: Master's Assignment
Contacts: André Kokkeler
Location: CAES, University of Twente


Research question

How can the distributed digital processing on a digital amplifier controller IC be made as versatile as possible?



Axign is a young start-up company that develops mixed-signal controller ICs. These ICs feature a combination of digital loop-filters and very linear ADCs to enable tight control of external power stages and achieve high performance at low costs. Axign’s first product will be an 8-channel data converter and controller IC with PWM outputs for digital audio amplifiers. The digital filters on this IC are implemented with distributed processing elements


The subject of this assignment is to investigate how the reconfigurability of these processing elements can be improved to enable more versatile applications. A suitable balance has to be found between configurability and hardware costs. Possible directions for investigations can be (but are not limited to):

  • Can a simple on-chip network have benefits for the control-path (and possibly the data-path)?
  • Is it possible to re-use the processing elements more efficiiently for e.g. multiple filter stages?
  • Currently, a butterfly structure is used to combine outputs of various channels. This structure might be extended to include other operations?
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