16-Channel UHF Beamforming Demonstrator

Type: Bachelor Assignment
Contacts: Tom Bruintjes, Jordy Huiting
Location: CAES, University of Twente

The aim of this assignment is to build a 16 channel beamformer [1] for demonstration and test purposes. To design such a platform we will (re)use the frontend of a Nedap EPC-gen2 RFID label reader designed to work in the 900MHz UHF band This frontend provides eight 12-bit digitized serial channels. However, we wish to have a 16-channel beamformer. Two frontends will therefore be combined with a custom PCB, designed by CAES, to provide the desired amount of channels. The frontend data will be fed to a Virtex-4 FPGA from Xilinx for further digital processing.

The digital processing involves correct recovery of the frontend data, filtering if this turns out to be needed and beamforming the 16 channels in order to localize an RFID tag. If time permits the assignment could include a (to be determined) visualization of the digital beamforming going on inside the FPGA. A few possibilities would be to stream tag location information to a PC or show the tag's location on an LCD screen connected directly to the FPGA.

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An optimizing compiler backend for a processor executing lazy functional languages.

Type: Master's Assignment
Contacts: Arjan BoeijinkJan Kuper
Location: CAES, University of Twente


We are designing the PilGRIM processor specialized for executing lazy functional languages (PilGRIM is an acronym for Pipelined Graph Reduction Instruction Machine). The PilGRIM attempts to remove performance overheads caused by functional abstractions using the many extra transistors that are available nowadays. We also focus on minimizing the amount of memory accesses and try to keep more data local, because the costs of a memory access in terms of energy and latency are big.

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Functional Hardware Descriptions - CPU Design and Analysis

Type: Master's Assignment
Contacts: Christiaan BaaijJan Kuper
Location: CAES, University of Twente

The basic building blocks for hardware circuits can be directly modeled as (mathematical) functions. Functional languages, which lend themselves very well to creating and composing functions, can as such be used to describe hardware circuits in a very natural way. In the CAES group, we developed a new functional hardware description language called CλaSH, that borrows both the syntax and semantics from the functional programming language Haskell. It allows for structural descriptions of synchronous hardware, using normal Haskell syntax combined with a selection of built-in functions for operations like addition, or list operations. More complex constructions, like higher-order functions and polymorphism, are fully supported. The hardware descriptions made in CλaSH can be translated to synthesizable VHDL by the CλaSH compiler.

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Register-Transfer-Level Design in Matlab

Type: Master's Assignment
Contacts: Sabih Gerez
Project:  
Location: CAES, University of Twente

Hardware can be specified at several abstraction levels, from system-level descriptions using e.g. data-flow graphs to transistor-level descriptions in terms voltages and currents. A very common abstraction level is the register-transfer level (RTL). It describes hardware as a synchronous system in which all registers are updated at the same (rising) clock edge. The registers store the state of the system. RTL specifications describe how the next state can be computed from the current state and the circuit's primary inputs as well as how the primary outputs can be computed from the current state and the inputs.  A language as VHDL is typically used for RT-level descriptions. Logic synthesis tools automatically translate RTL descriptions into logic gates and their interconnections.

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