High speed FPGA based transceiver design

Type: Master's Assignment
Contacts: Marco Bekooij
Project:  
Location: CAES, University of Twente

A narrow band RF receiver front-end has been interfaced with a Virtex 6 FPGA board such that software defined radio receiver applications can be prototyped on an embedded multiprocessor system. However, the generation of RF signals is not yet possible with this system.

The objective of this graduation project is the creation of a transceiver by adding a high speed digital-to-analog converted (5GS/s) into the system. By adding also appropriate upsampling filters it should become possible to transmit RF signals without additional analog components. Design options should be explored and the achieved performance of the system should be compared with theoretical results. Evaluation of the system could for example be carried out by adding an FM modulator in digital hardware. This FM modulator can be interfaced with for example a GMSK transceiver that is executed in software on the multiprocessor system.

 

 

MPSoC video feature extraction and tracking

Type: Master's Assignment
Contacts: Marco Bekooij
Project:  
Location: CAES, University of Twente

A 16 core homogeneous multiprocessor systems on a Virtex 6 FPGA has been developed in the CAES group. This multiprocessor systems is extensively used in the Real-time systems 2 course to obtain experience with the programming of multiprocessor systems. The performance of this system has shown to be sufficient for games and software defined radios. However, whether the performance of the system is sufficient for the extraction of features from video streams is questionable.

The objective of this graduation project is to extend the hardware of the multiprocessor system such that feature extraction, i.e. recognition and tracking of objects, from a real-time video stream becomes feasible. This could require the design of hardware accelerators and the design of application specific data-caching schemes. A potentially attractive flow from C-code can be created using the Vivado design suite of Xilinx. The use of a Virtex 7 FPGA should be considered if the available memory and logic of the Virtex 6 FPGA is insufficient.

Optimizing schedule for a smart heating system

Type: Master's Assignment / Internship
Contacts: Albert Molderink, This email address is being protected from spambots. You need JavaScript enabled to view it.
Location:

CAES, University of Twente / Bosch

Description 

  • 3-9 months internship or M.Sc. thesis opportunity
  • Optimization of the scheduling of the heating system / a smart heating system / Smart Thermostat (heating setpoints during night, learn behavior, zone control, etc.)
  • Analyzing the status of the device using already available sensors (flame quality, life time, wearing)
  • Optimization of the behavior of the heating system (appliance/flame efficiency)

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Smart solutions to minimize CPU peak load

Type: Master's Assignment / Internship
Contacts: Albert Molderink, This email address is being protected from spambots. You need JavaScript enabled to view it.
Location:

CAES, University of Twente / Bosch

Description 

  • 3-9 months internship or M.Sc. thesis opportunity
  • Investigation on smart solutions to minimize CPU peak load
  • Analysis of different types of operating systems for suitability in event driven applications
  • Close collaboration with software developers at Bosch Thermotechnik
  • Work on real world problems

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