Analysis and Design of a Dependability Manager for Self-Aware Dependable SoCs

Type: Master's Assignment
Contacts: Ahmed Ibrahim, MSc., Dr. ir. Hans Kerkhoff
Project:  
Location: CAES, University of Twente
 

Keywords:

Computer Architecture, Hardware-Software co-design, ASIP.

Prerequisite knowledge:

Computer architecture, strong knowledge of digital design and VHDL, FPGA design flow, basic knowledge of Java and C, basic compiler concepts, basic TCL understanding.

Description:

The current trend of aggressive technology scaling and the increasing reliance on design reuse and automation lead to very complex System-on-Chips (SoCs). Testing and debugging of such complex SoCs is a challenging task. Consequently, embedded instruments have been increasingly integrated into SoCs, not only in order to help in testing and debugging, but also for lifetime dependability management.

In the CAES-TDT group we investigate the on-chip access of embedded instruments for smart, self-aware dependable SoCs. A Dependability Manager (DM) is a system-level IP that is able to access the distributed embedded instruments via reconfigurable scan networks, and use the instruments information for executing dependability applications. One can think of the DM as an Application Specific Instruction-set Processor (ASIP) that executes dependability procedures written in a high level language (C/C++/C#/Java…) along with the instruments access procedures written in IEEE 1687 Procedural Description Language (PDL).

In this MSc. thesis it is required to investigate, design and implement a fully operational Dependability Manager. The DM mainly consists of a processor in its core (e.g. MIPS) and several coprocessors for the network operations (a conceptual architecture -not necessarily adopted- is given in Figure 1). In addition, the student will extend an already developed Procedural Description Language (PDL) cross-compiler [1], in order to enable defining instruments interrupts and linking PDL object code with the compiled high level language dependability procedures and interrupt service routines (Figure 2).

 

Figure1. Conceptual architecture of the DM

Figure 2. Conceptual compilation flow of the dependability applications

The following tasks are to be performed (along with any other necessary ones) within this thesis work:

  • Literature review on ASIP design methodologies.
  • Analyze the different requirements for the different dependability applications (e.g. self-awareness/adaptiveness, online BIST, fault management), and chose an appropriate high level language for their implementation.
  • Perform a complete hardware-software co-design based on the performed analysis. Then implement your design in both hardware and software.
  • An FPGA demonstrator including the DM and a non-trivial iJTAG network will be performed by the end of the thesis showing a working DM + the compilation flow for a number of dependability applications utilizing instruments interrupts.

Successful completion of this thesis could lead into a joint publication in a very active research area (iJTAG and embedded instrumentation).

For more information, please contact Ahmed Ibrahim: This email address is being protected from spambots. You need JavaScript enabled to view it., Tel: +31534894734, Room: ZI 5034.

References:

[1] M. Zakiy, “HW-SW co-Design of an On-Chip IJTAG Dependability Processor”, University of Twente, MSc. Thesis, 2016

[2] Ahmed Ibrahim and Hans G. Kerkhoff, “Analysis and design of an on-chip retargeting engine for IEEE 1687 networks” 21st IEEE European Test Symposium (ETS), 2016, pp. 1-6.

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