MODERN: Mapping On Demand for EneRgy-efficient ComputatioN

This project will develop new methodologies to minimise the energy required to achieve a given rate of computation for a given technology. It brings together a broad base of research expertise from both embedded and mainstream computing systems, recognises the converging requirements across these domains and exploits the innovations from each. A key element of the project is a hardware virtualisation layer that supports both data driven scheduling and the dynamic adaptation in the mapping of computational components onto computing resources. This dynamic mapping will optimise and balance energy dissipation over the computational, communication and memory resources, while meeting non-functional requirements of throughput and latency. The mapping process will be supported by analysis, models and algorithms. The models will be developed for power optimisation under throughput and latency constraints. The anticipated target for these computations will be heterogeneous collections of cores, clusters of cores, programmable logic and dedicated hardware. A significant amount of engineering effort will be required to demonstrate the feasibility of mapping the concurrency captured in the virtualisation layer onto this highly heterogeneous fabric. This must be achieved at a granularity that amortises any mapping related overheads and will require some form of program transformation. Energy efficiency will be achieved using a variety of techniques, such as load balancing using distributed frequency scaling, managing the locality of communications through the development of weak memory consistency models together with optimal mapping and a resource management layer that provides distributed control over the powering of computational resources. Using these techniques the energy consumption of processing can be reduced by up to three orders of magnitude.


The techniques and technology that will be developed in this project are generic and are applicable across a wide range of application domains. These includes embedded systems (although hard real-time poses some difficulties due to the essentially statistical nature of dynamic mapping), commodity processors including mobile devices and even large data centres, where significant power savings can be made through the exploitation of low-power components, where applicable, in a heterogeneous mix of computing resources. The project is curiosity driven and will not be developing an end-user product. However, we anticipate prototyping implementations of the virtualisation layer across a range of architecture and providing a range of system services to support mapping and scheduling strategies. In addition we will explore techniques for efficient code generation, including code transformation to
manage granularity. These will be generic implementations where possible and will be made publically available as demonstrators on a variety of implementation platforms. These will include the Distributed ASCI Supercomputer, which addresses some of the project's concerns in that it increases the hardware diversity (multi-cores, special architectures like GPUs, MPSoCs, FPGAs) compared to previous DAS clusters. In addition, we expect to have access to an Intel Single-chip Cloud Computer (SCC) to demonstrate some of the techniques that rely on distributed energy management. SCC is the first multi-core platform to provide programmed access to distributed frequency and voltage scaling.

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